tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 161

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Protective Circuit Registers [Addresses (PMD1 and PMD2)]
(01FBFH)
(01FEFH)
EMGCRB
(01FB1H)
(01FE1H)
EMGCRA
(01FB0H)
(01FE0H)
EMGREL
Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGREL register because this
Note: If during overload protection the port output state in two or more upper phases is on, all lower phases are disabled and all
Note 1: An instruction specifying a return from the EMG state is invalid if the
Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGCRB or EMGCRA register
register is write only.
upper phases are enabled for output; when two or more lower phases are on, all upper phases are disabled and all lower
phases are enabled for output.
7 to 0
7 to 4
3, 2
because these registers contain write-only bits.
7
6
5
4
1
0
2
1
0
RTCL
D7
7
7
7
EMGREL
RTCL
RTPWM
RTTM1
CLST
CLMD
CNTST
CLEN
CLCNT
EMGST
RTE
EMGEN
RTPWM
D6
6
6
6
CLCNT
RTTM1
EMG disable
Return from overload protec-
tive state
Enable/Disable return from
overload protective state by
PWM sync
Enable/Disable return from
overload protective state by
timer 1
Overload protective state
Select output disabled phases
during overload protection
Stop PWM counter during over-
load protection
Enable/Disable overload pro-
tective circuit
Overload protection sampling
number of times.
EMG protective state
Return from EMG state
Enable/Disable EMG protective
circuit
D5
5
5
5
CLST
D4
4
4
4
D3
3
3
3
CLMD
Page 151
EMGST
Can disable by writing 5AH and then A5H.
0: No operation
1: Return from protective state
0: Disable
1: Enable
0: Disable
1: Enable
0: No operation
1: Under protection
00: No phases disabled against output
01: All phases disabled against output
10: PWM phases disabled against output
11: All upper/All lower phases disabled against output (Note)
0: Do not stop
1: Stop the counter
0: Disable
1: Enable
2
0: No operation
1: Under protection
0: No operation
1: Return from protective state (Note 1)
0: Disable
1: Enable
2
D2
2
2
/fc × n ( n = 1 to 15, 0 and 1 are set as 1 at 20 MHz )
2
CNTST
RTE
D1
1
1
1
EMG
EMGEN
CLEN
D0
0
0
0
input is “L”.
(Initial value: 0000 0000)
(Initial value: 0000 0000)
(Initial value: 0000 *001)
TMP88CS43FG
R/W
R/W
R/W
R/W
W
W
W
R
R