tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 147

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

MTCRB
MTCRA
7, 6, 5
7
5
3
2
1
4
3
2
1
0
13.4.1.1 Timer Circuit Register Functions
MCAP
CMP1
CMP2
CMP3
SWRES
DBOUT
PDCCP
RBPDC
RBTM3
SWCP
TMOF
TMCK
TMEN
CLCP
RBCL
Mode capture
Timer 1 (commutation)
Timer 2 (position detection start)
Timer 3 (overflow)
(commutation)
(position detection start)
detection interrupt
Debug output (P67, P77)
imer 1 interrupt
imer 2 interrupt
imer 3 interrupt or position
Debug output
Mode timer overflow
Capture mode timer by over-
load protection
Capture mode timer in soft-
ware
Capture mode timer by posi-
tion detection
Select clock
Reset mode timer from Timer
3
Reset mode timer by over-
load protection
Reset mode timer in software
Reset mode timer by position
detection
Enable/disable mode timer
Figure 13-8 DBOUT Debug Output Diagram
Debug output can be produced by setting this bit to 1. Because interrupt signals to the
interrupt control circuit are used for each interrupt, hardware debugging without software
delays are possible. See the debug output diagram (Figure 13-8). Output ports: P67 for
PMD1, P77 for PMD2.
This bit shows that the timer has overflowed.
When this bit is set to 1, the timer value can be captured using the overload protection
signal (CL) as a trigger.
When this bit is set to 1, the timer value can be captured in software
(e.g., by writing to this register).
When this bit is set to 1, the timer value can be captured using the position detection sig-
nal as a trigger.
Select the timer clock.
When this bit is set to 1, the mode timer is reset by a trigger from Timer 3.
When this bit is set to 1, the mode timer is reset by the overload protection signal (CL) as
a trigger.
When this bit is set to 1, the mode timer is reset in software (e.g., by writing to this regis-
ter)
When this bit is set to 1, the mode timer is reset by the position detection signal as a trig-
ger.
The mode timer is started by setting this bit to 1. Therefore, Timers 1 to 3 must be set with
CMP before setting this bit. If this bit is set to 0 after setting CMP, CMP settings become
ineffective.
Position detection interval can be read out.
Timers 1 to 3 are enabled while the mode timer is operating. An interrupt can be gener-
ated once by setting the corresponding bit in this register. The interrupt is disable when an
interrupt is generated or the timer is reset. To use the timer again, set the register back
again even if data is same.
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TMP88CS43FG