tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 192

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15. Synchronous Serial Interface (SIO)
15.6 Transfer Mode
15.6.2 4-bit and 8-bit receive modes
data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word
of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the
number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is
generated to request that these data be read out. The data are then read from the data buffer registers by the
interrupt service program.
next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.
A wait will not be initiated if even one data word has been read.
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay
between the time when the interrupt request is generated and when the data received have been read.
interrupt service program.
cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has
ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiv-
ing is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIO-
INH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is
ignored, and it is not required to be read out.)
cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read
out.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The
When the internal clock is used, and the previous data are not read from the data buffer register before the
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
SCK pin
SIOSR<SIOF>
SO pin
during SIO do not use such DBR for other applications.
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans-
fer mode.
Figure 15-9 Transmiiied Data Hold Time at End of Transfer
MSB of last word
t
SODH
Page 182
= min 3.5/fc [s] (In the NORMAL, IDLE modes)
TMP88CS43FG