at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 208

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.5.5.1
Figure 22-6. Self-refresh Mode Behavior
208
SDRAMC_A[12:0]
SDRAMC_SRR
SDCKE
SDWE
SDCK
SDCS
AT91SAM9G20 Preliminary
Write
RAS
CAS
Self-refresh Mode
SRCB = 1
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register.
In self-refresh mode, the SDRAM device retains data without external clocking and provides its
own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM
device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device
is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh
mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)
and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to
the low-power SDRAM during initialization.
The SDRAM device must remain in self-refresh mode for a minimum period of t
remain in self-refresh mode for an indefinite period. This is described in
Self Refresh Mode
to the SDRAM Controller
Access Request
T
Figure
XSR
= 3
6384B–ATARM–15-Dec-08
22-6.
RAS
Row
and may