at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 615

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

35.9.11
Name:
Access Type: Read-only
• CMDRDY: Command Ready
0 = A command is in progress.
1 = The last command has been sent. Cleared when writing in the MCI_CMDR.
• RXRDY: Receiver Ready
0 = Data has not yet been received since the last read of MCI_RDR.
1 = Data has been received since the last read of MCI_RDR.
• TXRDY: Transmit Ready
0= The last data written in MCI_TDR has not yet been transferred in the Shift Register.
1= The last data written in MCI_TDR has been transferred in the Shift Register.
• BLKE: Data Block Ended
This flag must be used only for Write Operations.
0 = A data block transfer is not yet finished. Cleared when reading the MCI_SR.
1 = A data block transfer has ended, including the CRC16 Status transmission.
In PDC mode (PDCMODE=1), the flag is set when the CRC Status of the last block has been transmitted (TXBUFE already
set).
Otherwise (PDCMODE=0), the flag is set for each transmitted CRC Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
• DTIP: Data Transfer in Progress
0 = No data transfer in progress.
1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.
• NOTBUSY: MCI Not Busy
This flag must be used only for Write Operations.
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data
transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data
line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data
transfer block length becomes free.
6384B–ATARM–15-Dec-08
TXBUFE
ENDTX
UNRE
31
23
15
–
7
MCI Status Register
MCI_SR
RXBUFF
ENDRX
OVRE
DTOE
30
22
14
6
NOTBUSY
DCRCE
29
21
13
–
–
5
RTOE
DTIP
28
20
12
–
–
4
RENDE
BLKE
27
19
11
–
3
-
AT91SAM9G20 Preliminary
RCRCE
TXRDY
26
18
10
–
2
-
SDIOIRQB
RXRDY
RDIRE
25
17
–
9
1
SDIOIRQA
CMDRDY
RINDE
24
16
–
8
0
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