at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 797

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.3
44.2.3.1
6384B–ATARM–15-Dec-08
Reset Controller (RSTC)
RSTC: Reset During SDRAM Accesses
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data are ready to be read on the data bus. The SDRAM maintains the data until the clock
restarts.
If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
Example with libV3.
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
1. Avoid User Reset to generate a system reset.
2. Trap the User Reset with an interrupt.
• The main code:
• The C SYS handler:
Problem Fix/Workaround
//user reset interrupt setting
*AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN;
}
extern void soft_user_reset(void);
void sysc_handler(void){
// Configure AIC controller to handle SSC interrupts
AT91F_AIC_ConfigureIt (
// Enable SYSC interrupt in AIC
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
AT91C_BASE_AIC,
AT91C_ID_SYS,
AT91C_AIC_PRIOR_HIGHEST,
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
AT91SAM9G20 Preliminary
// System peripheral ID
// AIC base address
// Max priority
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