at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 800

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.6.2
44.2.6.3
44.2.6.4
44.2.7
44.2.7.1
44.2.8
44.2.8.1
44.2.9
44.2.9.1
800
AT91SAM9G20 Preliminary
System Controller (SYSC)
Two-wire Interface (TWI)
UHP
SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SYSC: Possible Event Loss when reading RTT_SR
TWI: RXRDY Flag is not reset by a SOFTWARE Reset
UHP: Non-ISO IN Transfers
Enable the pull-up on RK pin.
When the SSC receiver is used in the following configuration:
then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of
MCK/(2 x DIV).
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is
read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle an RTT event as an interrupt and should not poll RTT_SR.
The RXRDY Flag is not reset when a Software reset is performed.
After a Software Reset, the Register TWI_RHR must be read.
Conditions:
Consider the following sequence:
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6384B–ATARM–15-Dec-08