at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 43

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

6384B–ATARM–15-Dec-08
Exception Modes and Handling
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep-
tions according to the following priority order:
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort
occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and pro-
ceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to
resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer
error does not escape detection.
Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam-
ple, to service an interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
The register r13 is also banked across exception modes to provide each exception handler with
private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable
nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in
the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies
according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or
remove the requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be
completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as
invalid, but does not take the exception until the instruction reaches the Execute stage in the
• Reset (highest priority)
• Data Abort
• FIQ
• IRQ
• Prefetch Abort
• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
1. Preserves the address of the next instruction in the appropriate Link Register that cor-
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
responds to the new mode that has been entered. When the exception entry is from:
– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction
– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value
into LR (current PC(r15) + 4 or PC + 8 depending on the exception).
(current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the
program to resume from the correct place on return.
AT91SAM9G20 Preliminary
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