afs600 Actel Corporation, afs600 Datasheet - Page 108

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode for a system
that runs at 66 MHz.
The period of SYSCLK: t
Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK requirement. A higher
TVC leads to a higher ADCCLK period.
The minimum TVC is chosen so that t
computed by
From
first compute the post-calibration time, second the distribution time, and finally the STC setting.
Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be enabled and the
post-calibration time, t
The distribution time, t
The STC value can now be computed through
page 2-93
And so, STC will be rounded up to 3 to ensure the minimum conversion time is met. The sample time, t
STC of 3, is now equal to 0.36 µs.
The total sample time, using
The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is listed as follows:
*Note that no power-down after every conversion is chosen in this case; however, if the application is power-sensitive,
the MODE[2] can be set to '0', as described above, and it will not affect any performance.
2 -9 4
TVC[7:0]
STC[7:0]
MODE[3:0] = b'0100
Actel Fusion Programmable System Chips
Example
Table 2-47 on page
t
conv
t
with a t
sample
= 1
= 3
=
EQ
t
sync_read
=
2-15.
sample
t
conv
+
post-cal
–
distrib
SYSCLK
= 0x01
= 0x03
= 0x4*
of 0.35 µs, the STC can be computed.
t
t
sample
post-cal
2-105, minimum conversion for 10-bit mode is 1.8 µs. To compute STC, the calculation will
t
, is equal to 1.2 µs and can be computed using
ADCCLK
EQ
, can be computed by
= 1/66 MHz = 0.015 µs
+
–
t
2-19, can now be summated.
t
distrib
distrib
=
distrib
+
4
–
t
t
×
t
post-cal
distrib
sync_read
STC
(
1
and t
+
t
=
=
TVC
post-cal
+
EQ
N t
------------------ - 2
t
t
–
post-cal
t
ADCCLK
sync_write
sample
)
×
t
2-18. The sample time is equal to 0.32 µs. By rearranging
sync_write
×
EQ
ADCCLK
=
t
A d v a n c e d v 1 . 4
SYSCLK
2
can be run faster. The period of ADCCLK with a TVC of 1 can be
–
2-16. The post-calibration time is 0.24 µs.
×
=
t
ADCCLK
=
=
0.015 µs
=
=
1.8 µs 0.24 µs
0.35 µs
------------------ - 2
0.12 µs
10 0.12
4
×
×
(
=
1
–
+
+
0.24 µs
–
0.36 µs
1
)
=
×
=
1.2 µs
0.015 µs
2.85
–
EQ
+
1.2 µs
1.2 µs
2-17.
=
–
+
0.12 µs
0.15 µs
0.24 µs
–
+
0.15 µs
0.015 µs
=
0.32 µs
=
sample
1.85 µs
EQ 2-11 on
, with an
EQ 2-15
EQ 2-16
EQ 2-17
EQ 2-18
EQ 2-19