afs600 Actel Corporation, afs600 Datasheet - Page 50

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Voltage Regulator Power Supply Monitor (VRPSM)
As the functions of the VR Logic and Power System
Monitor work closely together to control the power-up
state of the FPGA core, these functions were combined
into a single VRPSM macro
The signals for the VRPSM macro are listed in
The PUB input comes from the PUB pin on the device and
Figure 2-30 • VRPSM Macro
Table 2-18 • Signals for VRPSM Macro
2 -3 6
Signal Name
PUB
VRPU
VRINITSTATE
RTCPSMMATCH
FPGAGOOD
PUCORE
Actel Fusion Programmable System Chips
Number of Bits
(Figure
1
1
1
1
1
1
2-30).
PUB
VRPU
VRINITSTATE
RTCPSMMATCH
Table
Direction
Output
Output
Input
Input
Input
Input
A d v a n c e d v 1 . 4
2-18.
can be pulled LOW by a signal external to the Fusion
device. This can be used to wake up the device. The
inputs VRINITSTATE and RTCPSMMTACH come from the
VR Init and RTC blocks, respectively, and either can
initiate a VR power-up. The detailed description is
available in the
Active low signal to power up the FPGA core via the 1.5 V
regulator.
In this reference design, PUB is on the top level, connected to an
external switch.
When this pin is at logic 1, the FPGA core will be turned off via
the voltage regulator.
This feature is not used in this reference design and is not shown
in the macro generated by SmartGen. If used, the signal enables
you to set your voltage regulator output at power-up (ON or
OFF).
This feature is not used in this reference design. If used, this
active high signal is driven by the RTC’s match signal to indicate
that the RTC counter value matches the pre-defined Match
register value set in SmartGen.
Logic 1 indicates that FPGA is logically functional.
Logic 1 indicates that FPGA is logically functional.
FPGAGOOD
PUCORE
Peripheral User
Function
Guide.