afs600 Actel Corporation, afs600 Datasheet - Page 28

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Clock Aggregation
Clock aggregation allows for multi-spine clock domains.
A MUX tree provides the necessary flexibility to allow
long lines or I/Os to access domains of one, two, or four
global spines. Signal access to the clock aggregation
system is achieved through long-line resources in the
central rib, and also through local resources in the north
and south ribs, allowing I/Os to feed directly into the
Figure 2-14 • Clock Aggregation Tree Architecture
2 -1 4
Actel Fusion Programmable System Chips
Tree Node MUX
Global Driver and MUX
Global Spine
Global Rib
A d v a n c e d v 1 . 4
I/O Access
Internal Signal Access
Global Signal Access
clock system. As
is contiguous.
There is no break in the middle of the chip for north and
south I/O VersaNet access. This is different from the
quadrant clocks, located in these ribs, which only reach
the middle of the rib.Refer to the
in Actel Fusion Devices
Figure 2-14
application note.
I/O Tiles
indicates, this access system
Using Global Resources