afs600 Actel Corporation, afs600 Datasheet - Page 67

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

SRAM and FIFO
All Fusion devices have SRAM blocks along the north side
of the device. Additionally, AFS600 and AFS1500 devices
have an SRAM block on the south side of the device. To
meet the needs of high-performance designs, the
memory blocks operate strictly in synchronous mode for
both read and write operations. The read and write
clocks are completely independent, and each may
operate at any desired frequency less than or equal to
350 MHz. The following configurations are available:
The Fusion SRAM memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag logic (FULL, EMPTY, AFULL, AEMPTY).
During RAM operation, addresses are sourced by the
user logic, and the FIFO controller is ignored. In FIFO
mode, the internal addresses are generated by the FIFO
controller and routed to the RAM array by internal
Figure 2-46 • Fusion RAM Block with Embedded FIFO Controller
• 4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two
• 512×9, 256×18 (two-port RAM—one read and one
• Sync write, sync pipelined/nonpipelined read
read, two write or one read, one write)
write)
Reset
FSTOP
ESTOP
WBLK
RBLK
REN
WEN
WCLK
RCLK
WD
FREN
CNT 12
CNT 12
FWEN
E
E
A d v an c ed v1 . 4
SUB 12
AEVAL
AFVAL
MUXes. Refer to
the implementation of the embedded FIFO controller.
The Fusion architecture enables the read and write sizes
of RAMs to be organized independently, allowing for
bus conversion. This is done with the WW (write width)
and RW (read width) pins. The different D×W
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
For example, the write size can be set to 256×18 and the
read size to 512×9.
Both the write and read widths for the RAM blocks can
be specified independently with the WW (write width)
and RW (read width) pins. The different D×W
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
Refer to the allowable RW and WW values supported for
each of the RAM macro types in
When a width of one, two, or four is selected, the ninth
bit is unused. For example, when writing 9-bit values and
reading 4-bit values, only the first four bits and the
second four bits of each 9-bit value are addressable for
read operations. The ninth bit is not accessible.
Conversely, when writing 4-bit values and reading 9-bit
values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte
order for read and write operations.
=
=
WD[17:0]
RCLK
WCLK
RADD[J:0]
WADD[J:0]
REN
WEN
FULL
AFULL
AEMPTY
EMPTY
Actel Fusion Programmable System Chips
Figure 2-46
RAM
RD[17:0]
for more information about
Table 2-27 on page
RD
2-55.
2-53