afs600 Actel Corporation, afs600 Datasheet - Page 47

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Table 2-16 • RTC ACM Memory Map
ACM_ADDR[7:0]
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
0x50
0x51
0x52
0x53
0x54
0x58
0x59
Note: Accessing RTC Registers: When reading the RTC count or match register, which operates in the XTLCLK domain, the appropriate
40-bit value is first copied to a capture register through clock synchronization circuitry, if and only if the least significant byte of
that set of register is addressed. Higher-order bytes of the same set of registers captured with the LSB can then be read on
immediately later read cycles. Higher-order bytes of that set of registers can be read in any order but must be read before
switching to a different set of registers to ensure data consistency. For example, RTC counter address ranges from 0x40 to 0x44,
register 0x40 must be accessed first before accessing addresses 0x41, 0x42, 0x43, and 0x44 to get the full 40-bit value.
Decimal
64
65
66
67
68
72
73
74
75
76
80
81
82
83
84
88
89
Register Name
MATCHREG0
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBITS0
MATCHBITS1
MATCHBITS2
MATCHBITS3
MATCHBITS4
COUNTER0
COUNTER1
COUNTER2
COUNTER3
COUNTER4
CTRL_STAT
TEST_REG
Counter bits 7:0
Counter bits 15:8
Counter bits 23:16
Counter bits 31:24
Counter bits 39:32
Match register bits 7:0
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
Individual match bits 15:8
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 39:32
Control (write) / Status (read) register
bits 7:0
Test register(s)
A d v an c ed v1 . 4
Description
Actel Fusion Programmable System Chips
Used to preload the counter to a
Test register(s)
specified start point. Default setting is
all zeroes.
The RTC uses a 40-bit register to
compare against the 40-bit counter
value to determine when a match
occurs. This 40-bit match register, like
the counter, is broken into 5 bytes
(MATCHREG0–4).
Each bit of the 40-bit counter is
compared to each bit of the 40-bit
match register via XNOR gates. These
40 match bits are partitioned into 5
bytes.
Control (write) / Status (read) register
bits 7:0
Use
2-33