afs600 Actel Corporation, afs600 Datasheet - Page 40

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

CCC Physical Implementation
The CCC circuit is composed of the following
Note: Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the
Figure 2-23 • PLL Block
2 -2 6
Actel Fusion Programmable System Chips
• PLL core
• 3 phase selectors
• 6 programmable delays and 1 fixed delay
• 5 programmable frequency dividers that provide
• 1 dynamic shift register that provides CCC dynamic
frequency multiplication/division (not shown in
Figure 2-23
configured
frequencies)
reconfiguration capability (not shown)
user's required frequencies.
CLKA
Fixed Delay
because
based
PLL Core
on
they
the
Four-Phase Output
are
user's
Programmable
(Figure
automatically
Delay Type 1
required
2-23):
A d v a n c e d v 1 . 4
CCC Programming
The CCC block is fully configurable. It is configured via
static flash configuration bits in the array, set by the user
in the programming bitstream, or configured through an
asynchronous
accessible from inside the Fusion device. The dedicated
shift register permits changes of parameters such as PLL
divide ratios and delays during device operation. This
latter mode allows the user to dynamically reconfigure
the PLL without the need for core programming. The
register file is accessed through a simple serial interface.
Select
Select
Select
Phase
Phase
Phase
dedicated
Programmable
Programmable
Programmable
Programmable
Programmable
Delay Type 2
Delay Type 2
Delay Type 1
Delay Type 2
Delay Type 1
shift
register,
GLB
GLA
GLC
YB
YC
dynamically