afs600 Actel Corporation, afs600 Datasheet - Page 229

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated
designed into every Fusion device. These circuits ensure
easy transition from the powered off state to the
powered up state of the device. The many different
supplies can power up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in
There are five regions to consider during power-up.
Fusion I/Os are activated only if ALL of the following
three conditions are met:
V
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
V
higher than ramp-down trip points. This specifically
built-in
oscillations and current surges. Note the following:
CC
CCI
CC
1. V
2. V
3. Chip is in the operating mode.
• During programming, I/Os become tristated and
• JTAG supply, PLL power supplies, and charge pump
Trip Point:
and V
Trip Point:
points
weakly pulled up to V
V
CC
CCI
PUMP
hysteresis
and V
> V
CCI
(Figure
supply have no influence on I/O behavior.
CC
ramp-up trip points are about 100 mV
power-up
CCI
– 0.75 V (typical).
are above the minimum specified trip
Figure 3-1 on page
3-1).
prevents
CCI
management
.
undesirable
3-6.
circuitry
power-up
A d v an c ed v1 . 4
is
Internal Power-Up Activation Sequence
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or
voltage regulators to ensure proper power-up behavior.
Power ramp-up should be monotonic at least until V
and V
activation level is specified as 1.1 V worst-case (see
Figure 3-1 on page 3-6
When PLL power supply voltage and/or VCC levels drop
below the VCC brownout levels (0.75 V ± 0.25 V), the PLL
output lock signal goes low and/or the output clock is
lost. Refer to the
application note for information on clock and lock
recovery.
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input
CCPLX
buffer activation
exceed brownout activation levels. The V
Actel Fusion Programmable System Chips
Power-Up/Down of Fusion FPGAs
for more details).
3-5
CC
CC