afs600 Actel Corporation, afs600 Datasheet - Page 205

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is
another differential I/O standard. It requires that one
data bit be carried through two signal lines. Like LVDS,
two pins are needed. It also requires external resistor
termination.
The full implementation of the LVDS transmitter and
receiver is shown in an example in
Figure 2-128 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-168 • Minimum and Maximum DC Input and Output Levels
Table 2-169 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-170 • LVPECL
DC Parameter
V
V
V
V
V
V
V
V
Input LOW (V)
1.64
Note: *Measuring point = V
Speed Grade
Std.
–1
–2
Note: For the derating values at specific junction temperature and voltage supply levels, refer to
CCI
OL
OH
IL
ODIFF
OCM
ICM
IDIFF
, V
Timing Characteristics
IH
OUTBUF_LVPECL
Commercial-Case Conditions: T
Applicable to Pro I/Os
Supply Voltage
Output LOW Voltage
Output HIGH Voltage
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
FPGA
Description
trip
. See
Table 2-87 on page 2-151
t
Input HIGH (V)
0.66
0.56
0.49
DOUT
N
P
Figure
Bourns Part Number: CAT16-PC4F12
1.94
J
= 70°C, Worst-Case V
100 Ω
100 Ω
2-128. The
Min.
0.625
1.762
0.96
1.01
300
1.8
0
A d v an c ed v1 . 4
3.0
2.14
1.82
1.60
for a complete table of trip points.
t
DP
187 W
Max.
1.27
2.11
0.97
1.98
2.57
3.3
building blocks of the LVPECL transmitter–receiver are
one transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVDS implementation
because the output standard specifications are different.
ZO = 50 Ω
ZO = 50 Ω
Measuring Point* (V)
CC
= 1.425 V, Worst-Case V
Cross point
Min.
0.625
1.762
1.06
1.92
1.01
300
0
100 Ω
t
0.04
0.04
0.03
DIN
3.3
Actel Fusion Programmable System Chips
Max.
1.43
2.28
0.97
1.98
2.57
N
P
3.6
Table 3-7 on page
FPGA
CCI
+
–
Min.
0.625
1.762
1.30
2.13
1.01
300
= 3.0 V
1.63
1.39
1.22
0
t
PY
V
3.6
REF
INBUF_LVPECL
3-9.
Max.
1.57
2.41
0.97
1.98
2.57
(typ.) (V)
3.9
–
Units
ns
ns
ns
Units
mV
V
V
V
V
V
V
V
2-191