m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 10

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

BA1 BA0
0
1
ESMT
Mode Register Definition
Mode Register Set (MRS)
latency, addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of
different applications. The default value of the register is not defined, therefore the mode register must be written in the power up
sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The
Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
* RFU should stay “0” during MRS cycle
Elite Semiconductor Memory Technology Inc.
0
0
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS
BA1
0
Operating Mode
BA0
0
EMRS Cycle
MRS Cycle
A11~ A7
RFU*
CAS Latency
A6
Preliminary
0
0
0
0
1
1
1
1
A5
0
1
0
1
0
0
1
1
A6
A4
0
1
0
1
0
1
0
1
CAS Latency
A5
Latency
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
2
3
A4
BT
A3
A3
0
1
Burst Length
A2
A2
0
0
0
0
1
1
1
1
Burst Length
Burst Type
Sequential
Interleave
Revision : 1.4
Publication Date : Sep. 2008
A1
A1
0
0
1
1
0
0
1
1
A0
A0
0
1
0
1
0
1
0
1
M53D128168A
Sequential Interleave
Reserve
Reserve
Reserve
Reserve
Reserve
Address Bus
Mode Register
2
4
8
Latency
Reserve
Reserve
Reserve
Reserve
Reserve
10/47
2
4
8