m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 17

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Read Interrupted by a Precharge
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
before the Read burst is complete. The following functionality determines when a Precharge command may be given during a
Read burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after t
4. For all cases above, t
Elite Semiconductor Memory Technology Inc.
C O M M A N D
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank
In all cases, a Precharge operation cannot be initiated unless t
satisfied. This includes Read with autoprecharge commands where t
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after t
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after t
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
Precharge command and a new Bank Activate command to the same bank equals t
with the result rounded up to the nearest integer number of clock cycles.
D Q S
D Q ' s
C L K
C L K
RP
.
R E A D
<Burst Length = 8, CAS Latency = 3>
0
1 t
RP
C K
is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
P r e c h a r g e
1
N O P
Preliminary
t
R P R E
t
D Q S C K
2
t
A C
D ou t 0
N O P
3
RP
D ou t 1
(RAS precharge time).
RAS
D o ut 2 D o ut 3 D ou t 4 D ou t 5 Do ut 6 D o ut 7
N O P
(min) [minimum Bank Activate to Precharge time] has been
4
RAS
I n t e r r u p t e d b y p r e c h a r g e
(min) must still be satisfied such that a Read with
N O P
5
RP
/ t
Revision : 1.4
Publication Date : Sep. 2008
N O P
CK
(where t
6
M53D128168A
CK
N O P
is the clock cycle time)
7
RP
N O P
17/47
where t
8
RP