ep1m120 Altera Corporation, ep1m120 Datasheet - Page 13

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Notes to
(1)
(2)
1.0 to 1.25 Gbps
Table 7. CDR-Mode Applications
1.0 Gbps
The V
Use AC-coupled LVDS or another I/O standard. The DC-coupled LVDS I/O standard provides performance up to
1.0 Gbps.
Data Rate
Table
CM
operating range for AC-coupled applications is from 0 to 0.7 V and from 1.8 to 2.4 V.
f
7:
DC-Coupled
Notes to
(1)
(2)
(3)
(4)
(5)
The multiplied reference clock is also used to synchronize and serialize at
the transmitter side.
Up to two different serial data rates are supported for input channels or
output channels. Received data must be non-return-to-zero (NRZ).
Table 7
supported data rates for each speed grade.
For more information on CDR, see
LVDS
v
(2)
EP1M350 devices have 18 individual receiver and transmitter channels. EP1M120
devices have 8 individual receiver and transmitter channels. Receiver and
transmitter channel numbers in parenthesis are for EP1M350 devices.
W = 1 to 12, 14, 16, 18, or 20
J = 3 to 12, 14, 16, 18, or 20
W does not have to equal J.
For every receiver channel in EP1M350 and EP1M120 devices, the ÷J recovered
clock can drive the priority column interconnect for use as a clock.
The two center channels adjacent to the HSDI PLLs (channels 4 and 5 for EP1M120
devices, channels 9 and 10 for EP1M350 devices) can drive the Mercury device’s
global clocks.
HSDI_CLK1 and HSDI_CLK2 pins must be differential. These clock pins drive
HSDI PLLs only. They do not drive to the logic array.
defines the support for CDR-mode applications.
Figure
DC-Coupled
LVPECL
4:
v
v
Mercury Programmable Logic Device Family Data Sheet
3.3-V PCML
DC-Coupled
v
v
CDR Mode
AN 130: CDR in Mercury
AC-Coupled
LVDS
v
v
(1)
AC-Coupled
LVPECL
v
v
Table 8
(1)
Devices.
3.3-V PCML
AC-Coupled
shows the
(1)
v
v
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