ep1m120 Altera Corporation, ep1m120 Datasheet - Page 52

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
52
Zero Bus Turnaround SRAM Interface Support
In addition to DDR SDRAM support, Mercury device I/O pins also
support interfacing with ZBT SRAM blocks at up to 200 MHz. ZBT SRAM
blocks are designed to eliminate dead bus cycles when turning a
bidirectional bus around between reads and writes, or writes and reads.
ZBT allows for 100% bus utilization because ZBT SRAM can read or write
on every clock cycle.
To avoid bus contention, the output t
low-impedance time (t
time (t
register, using a single general purpose PLL, enable the Mercury device to
meet ZBT t
Programmable Drive Strength
The output buffer for each Mercury device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL standard has
several levels of drive strength that can be controlled by the user. SSTL-3
class I and II, SSTL-2 class I and II, HSTL class I and II, and 3.3-V GTL+
support a minimum or maximum setting. The minimum setting is the
lowest drive strength that guarantees the I
maximum setting provides higher drive strength that allows for faster
switching and is the default setting. Using settings below the maximum
provides signal slew-rate control to reduce system noise and signal
overshoot.
drive strength control.
XZ
). Time delay control of clocks to the OE/output and input
Table 11
CO
and t
SU
shows the possible settings for the I/O standards with
ZX
times.
) is greater than the clock-to-high-impedance
ZX
delay ensures that the clock-to-
OH
/I
OL
of the standard. The
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