ep1m120 Altera Corporation, ep1m120 Datasheet - Page 29

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Clear & Preset Logic Control
LAB-wide signals control logic for the register’s clear and preset signals.
The LE directly supports an asynchronous clear and preset function. The
direct asynchronous preset does not require a NOT-gate push-back
technique. Mercury devices support simultaneous preset, or
asynchronous load, and clear. Asynchronous clear takes precedence if
both signals are asserted simultaneously. Each LAB supports one clear
and one preset signal. Two clears are possible in a single LAB by using a
NOT-gate push-back technique on the preset port. The Quartus II
Compiler automatically performs this second clear emulation.
In addition to the clear and preset ports, Mercury devices provide a chip-
wide reset pin (DEV_CLRn) that resets all registers in the device. Use of
this pin is controlled through an option in the Quartus II software that is
set before compilation. The chip-wide reset overrides all other control
signals.
Multi-Level FastTrack Interconnect
The Mercury architecture provides connections between LEs, ESBs, and
device I/O pins via an innovative Multi-Level FastTrack Interconnect
structure. The Multi-Level FastTrack Interconnect structure is a series of
routing channels that traverse the device, providing a hierarchy of
interconnect lines. Regular resources provide efficient and capable
connections while priority resources and specialized RapidLAB, leap line,
and FastLUT resources enhance performance by accelerating timing on
critical paths. The Quartus II Compiler automatically places critical design
paths on those faster lines to improve design performance.
This network of routing structures provides predictable performance,
even for complex designs. In contrast, the segmented routing in FPGAs
requires switch matrices to connect a variable number of routing paths,
increasing the delays between logic resources and reducing performance.
The Multi-Level FastTrack Interconnect consists of regular and priority
lines that traverse column and row interconnect channels to span sections
and the entire device length. Each row of LABs, ESBs, and I/O bands is
served by a dedicated row interconnect, which routes signals to and from
LABs, ESBs, and I/O row bands in the same row. These row resources
include:
Row interconnect traversing the entire device from left to right
Priority row interconnect for high speed access across the length of
the device
RapidLAB interconnect for horizontal routing that traverses a
10-LAB-wide region from a central LAB
Mercury Programmable Logic Device Family Data Sheet
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