ep1m120 Altera Corporation, ep1m120 Datasheet - Page 37

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A circuit using asynchronous RAM must generate
the RAM write enable (WE) signal while ensuring that its data and address
signals meet setup and hold time specifications relative to the WE signal.
In contrast, the ESB’s synchronous RAM generates its own WE signal and
is self-timed with respect to the global clock. Circuits using the ESB’s self-
timed RAM must only meet the setup and hold time specifications relative
to the global clock.
ESBs are grouped together in rows at the top and bottom of the device for
fast horizontal communication. The ESB row interconnect can be driven
by any ESB in the row. The row interconnect drives the ESB local
interconnect, which in turn drives the ESB ports. ESB outputs drive the
ESB local interconnect, which can drive row interconnect as well as all
types of column interconnect, including leap lines. The leap lines allow
fast access between ESBs and the adjacent LAB row.
When implementing memory, each ESB can be configured in any of the
following sizes for quad port and true dual-port memory modes: 256 16;
512 8; 1,024 4; 2,048
2; or 4,096 1. For dual-port and single-port
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modes, the ESB can be configured for 128 32 in addition to the list above.
For variable port width RAMs, any port width ratio combination must be
1, 2, 4, 8, or 16. For example, a RAM with data ports of width 1 and 16 or
2 and 32 will work, but not 1 and 32.
The ESB can also be split in half and used for two independent 2,048-bit
single-port or dual-port RAM blocks. For example, one half of the ESB can
be used as a 128 16 memory single-port memory while the other half can
be used for a 1,024 2 dual-port memory. This effectively doubles the
number of RAMs a Mercury device can implement for its given number
of ESBs. The Quartus II software automatically merges two logical
memory functions in a design into an ESB; the designer does not need to
merge the functions manually.
By combining multiple ESBs, the Quartus II software implements larger
memory blocks automatically. For example, two 256 16 RAM blocks can
be combined to form a 256
32 RAM block, and two 512 8 RAM blocks
can be combined to form a 512 16 RAM block. Memory performance
does not degrade for memory blocks up to 4,096 words deep. Each ESB
can implement a 4,096-word-deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic and its associated
delays. To create a high-speed memory block more than 4,096 words
deep, the Quartus II software will automatically combine ESBs with LE
control logic.
Altera Corporation
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