ep1m120 Altera Corporation, ep1m120 Datasheet - Page 45

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
If the same data is written into multiple locations in the memory, a CAM
block can be used in multiple-match or fast multiple-match modes. The
ESB outputs the matched data’s locations as an encoded or unencoded
address. In multiple-match mode, it takes two clock cycles to write into a
CAM block. For reading, there are 16 outputs from each ESB at each clock
cycle. Therefore, it takes two clock cycles to represent the 32 words from
a single ESB port. In this mode, encoded and unencoded outputs are
available. To implement the encoded version, the Quartus II software
adds a priority encoder with LEs. Fast multiple-match is identical to the
multiple-match mode, however, it only takes one clock cycle to read from
a CAM block and generate valid outputs. To do this, the entire ESB is used
to represent 16 outputs. In fast multiple-match mode, the ESB can
implement a maximum CAM block size of 16 words.
A CAM block can be pre-loaded with data during configuration, or it can
be written during system operation. In most cases, two clock cycles are
required to write each word into CAM. When don’t-care bits are used, a
third clock cycle is required.
f
For more information on CAM, see
Application Note 119 (Implementing
13
High-Speed Search Applications with APEX
CAM).
Driving into ESBs
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WREN, and RDEN signals on each port of the ESB. The fast global
signals and ESB local interconnect can drive the WREN and RDEN signals.
The fast global signals, dedicated clock pins, and ESB local interconnect
can drive the ESB clock signals. The ESB local interconnect is driven by the
ESB row interconnects which, in turn, are driven by all types of column
interconnects, including high-speed leap lines. Because the LEs drive the
column interconnect to the ESB local interconnect, the LEs can control the
WREN and RDEN signals and the ESB clock, clock enable, and asynchronous
clear signals.
Figure 25
shows the ESB control signal generation logic.
Altera Corporation
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