ep1m120 Altera Corporation, ep1m120 Datasheet - Page 50

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
Figure 27. IOE Configured for DDR Input
50
Column and
Column
Priority
Local Interconnect
Associated LAB
Local Fast
Two Row
Signals
Six Fast
Signals
Global
Dedicated
Clocks
Four
In Mercury device IOEs, the OE register is a multi-purpose register
available as a second input or output register. When using the IOE for
double data rate inputs, the input register and OE register are
automatically configured as input registers to clock input double rate data
on alternating edges. An input latch is also used within the IOE for DDR
input acquisition. The latch holds the data that is present during the clock
high times, driving it to the OE register. This allows the OE register and
input register to clock both bits of data into LEs, synchronous to the same
clock edge (either rising or falling).
DDR input.
Chip-Wide Reset
Input Register
OE Register
CLRN/PRN
D
ENA
D
ENA
CLRN/PRN
D
ENA
Latch
PRN
Q
Q
Q
Figure 27
Input Pin to Input
Register Delay
Priority Row (for Associated LAB Row)
Row (for Associated LAB Row)
shows an IOE configured for
VCCIO
Altera Corporation
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up