ep1m120 Altera Corporation, ep1m120 Datasheet - Page 18

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Mercury Programmable Logic Device Family Data Sheet
Figure 7. Mercury LE
Notes to
(1)
(2)
18
labclkena1
labclkena2
Chip-Wide
data4 (1)
FastLUT interconnect uses the data4 input.
LAB carry-out can only be generated by LE 4 and/or LE 10.
labclk1
labclk2
labpre
Reset
data1
data2
data3
labclr
Figure
LE Clock
7:
Enable
Clock Enable
Asynchronous
Clear/Preset/
Load Logic
Clock &
Select
LAB Carry-In
Carry-In1
Carry-In0
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock, clock enable, and clear control signals can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the register is bypassed and the output
of the LUT drives directly to the outputs of the LE.
Each LE has four data inputs that can drive the internal LUT. One of these
inputs has a shorter delay than the others, improving overall LE
performance. This input is chosen automatically by the Quartus II
software as appropriate.
Look-Up
(LUT)
Table
Chain
Carry
Synchronous
LAB-wide
Load
Carry-Out0
Carry-Out1
LAB Carry-Out (2)
Synchronous
Clear Logic
Load and
Synchronous
LAB-wide
Clear
Register Bypass
D
ENA
CLRN
PRN
Packed
Register Select
Q
Programmable
Register
Altera Corporation
FastLUT
Routing to next LE
to Local, Row, and
Column Routing
to Local, Row, and
Column Routing