ep1m120 Altera Corporation, ep1m120 Datasheet - Page 57

• Manufacturer Part Number: ep1m120
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Table 12. Mercury Supported I/O Standards
LVTTL
LVCMOS
2.5 V
1.8 V
3.3-V PCI
3.3-V PCI-X
LVDS
LVPECL
3.3-V PCML
GTL+
HSTL class I and II
SSTL-2 class I and II
SSTL-3 class I and II
AGP
CTT
I/O Standard
Table 12
Each regular I/O band row contains two I/O banks. The number of I/O
banks in a Mercury device depends on the number of I/O band rows. The
top I/O band contains four regular I/O banks specifically designed for
HSDI. The top I/O band banks and dedicated clock inputs support LVDS,
LVPECL, and 3.3-V PCML. 3.3-V PCML is an open-drain standard and
therefore requires external termination to 3.3 V. All other standards are
supported by all I/O banks. The top I/O banks 1, 2, 3, and 4 only support
non-HSDI I/O pins if the design does not use HSDI circuitry. If the design
uses any HSDI channel, banks 1, 2, 3, and 4 all do not support regular I/O
pins.
Additionally, the EP1M350 device includes the Flexible-LVDS feature,
providing support for up to 100 LVDS channels on all regular I/O banks.
Regular I/O banks in EP1M350 devices include dedicated LVDS input
and output buffers that do not require any external components except for
100- termination resistors on receiver channels.
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Differential
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
describes the I/O standards supported by Mercury devices.
Type
Mercury Programmable Logic Device Family Data Sheet
Voltage (V
Reference
Input
1.0
0.75
1.25
1.5
1.32
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(V)
REF
)
(V
Voltage
Supply
Output
CCIO
N/A
3.3
3.3
2.5
1.8
3.3
3.3
3.3
3.3
3.3
1.5
2.5
3.3
3.3
3.3
) (V)
Termination
(V
Voltage
Board
TT
3.3
1.5
0.75
1.25
1.5
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
) (V)
57
13