tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 133

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
9 SPE Mapper Registers
Contents
9 SPE Mapper Registers ..................................................................................................................................... 133
Contents
Table 144. SPE_VERSION_R, SPE Version and Identification Register (RO) ................................................... 134
Table 145. SPE_ONESHOT, One-Shot (R/W) .................................................................................................... 134
Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) ................................................... 134
Table 147. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) ................................................................................ 136
Table 148. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO) .................... 137
Table 149. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W) ....... 138
Table 150. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W) ........................................ 139
Table 151. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W) ............................................. 140
Table 152. SPE_RMON1—SPE_RMON5, Receive Monitor Values (RO) .......................................................... 140
Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) ........................ 140
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) ....................... 143
Table 155. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W) ....................................... 145
Table 156. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W) .......................................................... 145
Table 157. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W) ................................................ 145
Table 158. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W) .. 146
Table 159. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W) .......... 146
Table 160. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess
Table 161. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO) .......... 147
Table 162. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO) .................................. 147
Table 163. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) ................................... 148
Table 164. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W) ........................... 148
Table 165. SPE_SCRATCH_R, Scratch Pad (R/W) ........................................................................................... 148
Table 166. SPE Mapper Register Map ................................................................................................................ 149
Agere Systems Inc.
9.1 SPE Mapper Register Descriptions ........................................................................................................... 134
9.2 SPE Mapper Register Map ........................................................................................................................ 149
Zero Error Count (RO) ....................................................................................................................... 147
Table of Contents
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
TMXF28155/51 Super Mapper
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