tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 378

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
B3 BIP-8 Check. A B3 BIP-8 even parity is computed over all the incoming synchronous payload envelope bits of
the STS-3/STM-1/STS-1 signal after descrambling, and compared to the B3 byte received in the next frame. The
total number of B3 BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB3
page
counter is placed into holding registers TMUX_B3ECNT[1—3][15:0]
Depending on the value of SMPR_SAT_ROLLOVER
the internal counter will either roll over or stay at its maximum value until cleared.
Signal Label C2 Byte Monitor. The C2 byte per STS-1/STM-1 is stored in TMUX_C2MON[1—3][7:0]
on page101
(Table 99 on pag
must be identical for a programmed number frames prior to updating the C2 register. Any change to C2 byte moni-
tor is reported via the corresponding delta and mask register bits, TMUX_RC2MOND[1—3]
TMUX_RC2MONM[1—3]
In addition, there are programmable expected value(s) for the C2 bytes of each STS-1/STM-1 in
TMUX_C2EXP[1—3][7:0]
does not equal the expected C2 value in TMUX_C2EXP[1—3][7:0]), then a payload label mismatch defect may be
declared for that STS-1/STM-1 in TMUX_RPLMP[1—3]
C2 byte is all 0s, then the corresponding unequipped defect is declared in TMUX_RUNEQP[1—3] (
Note: The payload label mismatch and unequipped defects are mutually exclusive and unequipped takes priority.
The following table describes the conditions for generating payload label mismatch (TMUX_RPLMP[1—3]) and
unequipped defects (TMUX_RUNEQP).
378
TMUX_J1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in
TMUX_EXPJ1DMON[1—3][1—64][7:0]
mode, where the first expected byte, the byte following the 0x0A character, is written into the first location of
TMUX_EXPJ1DMON[1][7:0]. The TMUX will compare the incoming J1 sequence with the stored expected value,
setting the path trace identifier state bit(s), TMUX_RTIMP[1—3] if they are different. Any change to the path trace
identifier is reported in TMUX_RTIMPD[1—3], with interrupt mask bits, TMUX_RTIMPM[1—3].
TMUX_J1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in
EXPJ1DMON[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The
TMUX compares the incoming J1 sequence with the stored expected value, setting the state register bit(s),
TMUX_RTIMP[1—3], if they are different. Any change to path trace identifier is reported in register bits,
TMUX_RTIMPD[1—3], with interrupt mask bits, TMUX_RTIMPM[1—3].
TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined.
95), is counted. Upon the configured performance monitor (PM) interval, the value of the internal running
). Each register will be updated after a number, determined by the value in TMUX_CNTDC2[3:0]
e99), of consecutive frames of identical C2 bytes for a given STS-1/STM-1, i.e., the 8-bit pattern
(Table 87 on pag
(Table 100 on page100
(Table 134 on page122
e89).
(continued)
). If the current value of a C2 byte in TMUX_C2MON[1—3][7:0]
(Table 67 on pa
(Table 92 on page92
,
Table
(Table 126 on page119
ge68) in the microprocessor interface block,
135, and
). Also, if the current value of a
Table
136), in SONET framing
(Table
) and then cleared.
Agere Systems Inc.
83) and
Table
(Table 95 on
May 2001
(Table 104
92).