tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 144

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
9 SPE Mapper Registers
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (continued)
144
Address
0x3001C
0x3001D 15:8
0x3001E 15:8
Bit
7:0
5
4
3
2
1
0
7
6
5
4
3
SPE_TUNEQ_PRDIINH Transmit Path Unequipped RDI Inhibit. Control bit, when
SPE_NPI_BYTE2[7:0]
SPE_NPI_BYTE1[7:0]
SPE_TPLM_PRDIINH
SPE_TLOP_PRDIINH
SPE_TTIM_PRDIINH
SPE_TPOAC_H4
SPE_TPOAC_C2
SPE_TPOAC_K3
SPE_TPOAC_F2
SPE_TPOAC_J1
SPE_TPOAC_F3
SPE_TPRDIINS
Name
—
(continued)
Transmit POAC K3 Byte Control. Control bit, when 0, the
default value is inserted into the K3 byte in the transmit
frame. When 1, the TPOAC value is inserted in the K3 byte.
Transmit POAC H4 Byte Control. Control bit, when 0, the
default value is inserted into the H4 byte in the transmit
frame. When 1, the TPOAC value is inserted in the H4 byte.
Transmit POAC F3 Byte Control. Control bit, when 0, the
default value is inserted into the F3 byte in the transmit
frame. When 1, the TPOAC value is inserted in the F3 byte.
Transmit POAC F2 Byte Control. Control bit, when 0, the
default value is inserted into the F2 byte in the transmit
frame. When 1, the TPOAC value is inserted in the F2 byte.
Transmit POAC C2 Byte Control. Control bit, when 0, the
default value is inserted into the C2 byte in the transmit
frame. When 1, the TPOAC value is inserted in the C2 byte.
Transmit POAC J1 Byte Control. Control bit, when 0, the
default value is inserted into the J1 byte in the transmit
frame. When 1, the TPOAC value is inserted in the J1 byte.
Transmit NPI Byte 2. Programmable value for NPI byte 2 to
be inserted into the NPI byte location.
Transmit NPI Byte 1. Programmable value for NPI byte 1 to
be inserted into the NPI byte location.
Reserved.
Transmit RDI Software Insert. When 1, the value in
SPE_TG1DINS[3:1] is inserted into G1[3:1] in the transmit
frame; otherwise, hardware insert is enabled for RDI-P inser-
tion.
Transmit Trace Indicator Mismatch RDI Inhibit. Control
bit, when 1, the TIM failure will not contribute to the auto-
matic insertion of RDI-P; otherwise, the associated alarm
contributes to the generation of RDI-P.
Transmit Path Label Mismatch RDI Inhibit. Control bit,
when 1, the PLM failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contrib-
utes to the generation of RDI-P.
1, the unequipped failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contrib-
utes to the generation of RDI-P.
Transmit Loss of Pointer RDI Inhibit. Control bit, when 1,
the loss of pointer failure will not contribute to the automatic
insertion of RDI-P; otherwise, the associated alarm contrib-
utes to the generation of RDI-P.
Function
Agere Systems Inc.
May 2001
Default
Reset
0x00
0
0
0
0
0
0
0
0
1
0
0
0
0