tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 396

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
Contents
18 SPE Mapper Functional Description ............................................................................................................... 396
396
18.1 Introduction ............................................................................................................................................. 398
18.2 Features ................................................................................................................................................. 398
18.3 SPE Mapper Functional Block Diagrams ............................................................................................... 399
18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems) ............................................. 402
18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems) ............................................. 402
18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia / ANSI Standards Based Systems) ..................... 403
18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems) ................................................. 403
18.8 SPE Mapper Basic Configuration ........................................................................................................... 403
18.9 DS3 Configuration .................................................................................................................................. 403
18.10 Phase Detector for External DS3 PLL .................................................................................................. 404
18.11 Serial STS-1 SPE Channel (NSMI) ...................................................................................................... 405
18.12 TMUX Interface to the SPE Mapper ..................................................................................................... 406
18.13 PATH Termination Block ...................................................................................................................... 406
18.14 SPE Mapper Receive Direction Requirements ..................................................................................... 410
18.15 Transmit Direction (to SONET/SDH Line) ............................................................................................ 420
18.16 POAC Insert ......................................................................................................................................... 423
18.17 AIS Path Generation ............................................................................................................................. 424
18.9.1 DS3 M13 ...................................................................................................................................... 404
18.9.2 DS3 Loopback Channel ............................................................................................................... 404
18.9.3 DS3 Clear Channel from External Pins ........................................................................................ 404
18.13.1 Pointer Interpretation Block ....................................................................................................... 407
18.14.1 Loss of Clock and Loss of Sync Monitors ................................................................................. 411
18.14.2 J1 Monitor .................................................................................................................................. 411
18.14.3 B3 BIP-8 Check ......................................................................................................................... 412
18.14.4 Signal Label C2 Byte Monitor .................................................................................................... 412
18.14.5 Path User Byte F2 Monitor ........................................................................................................ 413
18.14.6 Path User Byte F3 Monitor ........................................................................................................ 414
18.14.7 N1 Monitor ................................................................................................................................. 414
18.14.8 K3 Byte Monitor ......................................................................................................................... 415
18.14.9 AIS-P and RDI-P Detect ............................................................................................................ 415
18.14.10 REI-P Detect ........................................................................................................................... 416
18.14.11 Signal Degrade BER Algorithm ............................................................................................... 416
18.14.12 Signal Fail BER Algorithm ....................................................................................................... 417
18.14.13 POAC Drop ............................................................................................................................. 418
18.14.14 Insertion of AIS-P .................................................................................................................... 419
18.15.1 PATH Insertion Block ................................................................................................................ 420
18.15.2 Loss of Clock and Loss of Sync Detectors ................................................................................ 421
18.15.3 J1 Byte Insert ............................................................................................................................ 421
18.15.4 B3 BIP-8 Calculation and Insert ................................................................................................ 421
18.15.5 C2 Signal Label Byte Insert ....................................................................................................... 421
18.15.6 REI-P G1(7:4) Insert .................................................................................................................. 421
18.15.7 Path RDI (RDI-P) Insert ............................................................................................................. 422
18.15.8 F2 Byte Insert ............................................................................................................................ 422
18.15.9 H4 Insert Control ....................................................................................................................... 422
18.15.10 F3 Byte Insert .......................................................................................................................... 422
18.15.11 K3 Insert Control Parameters .................................................................................................. 422
18.15.12 N1 Insert Control Parameters .................................................................................................. 423
Table of Contents
Agere Systems Inc.
May 2001
Page