tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 38
tmxf28155
Manufacturer Part Number
tmxf28155
Description
Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
Manufacturer
ETC-unknow
Datasheet
1.TMXF28155.pdf
(606 pages)
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TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
5 Timing Characteristics
(continued)
Table of Contents
(continued)
Tables
Page
Table 38. PSB Interface Receive Timing Characteristics ...................................................................................... 48
Table 39. NSMI (Mode 1) Input Clock Specifications ............................................................................................ 49
Table 40. Input Timing Specifications .................................................................................................................... 49
Table 41. Output Timing Specifications ................................................................................................................. 49
Table 42. SMI (Mode 2) Input Clock Specifications ............................................................................................... 49
Table 43. Input Timing Specifications .................................................................................................................... 50
Table 44. Output Timing Specifications ................................................................................................................. 50
Table 45. Framer Only Mode Clock Specifications ............................................................................................... 51
Table 46. Framer Mode Only Input Timing Specifications ..................................................................................... 52
Table 47. Framer Mode Only Output Timing Specifications .................................................................................. 52
Table 48. Framer—LIU Mode Clock Specifications ............................................................................................... 53
Table 49. Framer—LIU Mode Input Timing Specifications .................................................................................... 54
Table 50. Framer—LIU Mode Output Timing Specifications ................................................................................. 54
Table 51. Microprocessor Interface Synchronous Write Cycle Specifications ...................................................... 55
Table 52. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................... 56
Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................... 58
Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................... 60
Table 55. Input Timing Specifications .................................................................................................................... 60
Table 56. Output Timing Specifications ................................................................................................................. 61
38
Agere Systems Inc.
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