tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 495

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
(continued)
21.11.1 Link Count Selection
The link count is specified by programming FRM_R_LINKCNT[4:0] in FRM_SGR1, receive signaling global register
1 (R/W),
Table 359 on page262
, bits [14:10]. The reset value is 28, which is appropriate for a 28 link DS1 applica-
tion. A value of 21 is appropriate for a 21 link CEPT application. If the application mixes DS1 and CEPT links or the
TDM clock supplied to the framer section is less than 51.84 MHz, this value should match the terminal count set in
FRM_FGR2, framer global register 2 (R/W),
Table 306 on page246
, bits [7:0].
21.12 Other Receive Signaling Global Features
21.12.1 Support of Automatic Signaling Freeze on Framing Bit Errors
By default, signaling extraction from a particular link will halt when the appropriate alignment has been lost. In order
to guarantee that signaling freeze takes place as soon as possible, FRM_R_AFZFBE in FRM_SGR1, Receive Sig-
naling Global Register 1 (R/W),
Table 359 on pa
ge262, bit 1 must set to 1. When enabled, FRM_R_AFZFBE halts
signaling extraction for 32 frames upon detection of a frame bit error. This configuration bit is applicable to DS1,
CEPT, and CMI type frames and for signaling extracted from the receive line or the VT mapper interface. When
FRM_R_AFZFBE is enabled, the receive signaling debounce feature must also be enabled. The FRM_R_SIGDEB
feature is enabled in FRM_RSLR33, Receive Signaling Link Register 33 (R/W),
Table 374 on pag
e269, bit 5.
21.12.2 Support of Change of Signaling State FIFO
Signaling can be terminated in the framer section of the Super Mapper by polling FRM_RSLR0—FRM_RSLR31,
Receive Signaling Link Registers 0—31 (R/W),
Table 372 on page 268
for each link. An alternative method is to
enable the operation of a signaling change of state FIFO. In doing so, the host will be interrupted when there have
been signaling state changes which need to be processed. In order to enable the operation of the signaling change
of state FIFO, set FRM_R_SCOSEN in FRM_SGR2, Receive Signaling Global Register 2 (R/W),
Table 360 on
page
262, bit 15 to 1.
The FIFO is located at signaling receive global register 3. The word read by the host has the following format.
Table 581. Signaling Receive Global Register 3, Bit Definition
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
M
V
L4
L3
L2
L1
L0
TS4
TS3
TS2
TS1
TS0
D
C
B
A
The data read by the host indicates the link number (L[4:0]), time slot number (TS[4:0]) and the signaling informa-
tion for a time slot whose value has changed. The word read by the host will also indicate whether or not the entry
is valid (V = 1) and whether or not there are more entries yet to be read (M = 1). A word with V set to 0 indicates
that the FIFO is empty. The signaling code presented will reflect the associated GF value programmed by the host.
The unused signaling bits will be set to 0. For example, if the time slot is programmed for 4-state signaling, the D
and C bits will be set to 0. The A and B bit will identify the valid signaling code.
This feature can be used in combination with any other feature (i.e., debounce).
When the change of state FIFO is enabled, the host will be interrupted when one of two conditions is satisfied. If
the number of entries in the FIFO exceed the threshold programmed by the host or if there are valid entries to be
processed and the signaling interrupt timer has expired, then the host will be interrupted.
The host sets the FIFO depth threshold by programming FRM_R_SCOSDTH[9:0] in FRM_SGR2, Receive Signal-
ing Global Register 2 (R/W), bits [9:0]. The depth of the FIFO is 672, which is sufficient to store an entry for every
time slot processed by the 28-link framer. The timer interval is selected by programming FRM_R_SCOSTTH[15:0]
in FRM_SGR3, Receive Signaling Global Register 3 (R/W),
Table 361 on page
263, bits [15:0]. The timer incre-
ments are 125 µs and the maximum interval possible is 8 s. The default setting for the depth and timer threshold is
0, which results in the host being interrupted whenever an entry is made into the FIFO.
If the FIFO overflows, the processor will immediately be interrupted. The current contents of the FIFO will be lost
however, subsequent entries will be stored normally.
The host can poll the change of state FIFO without the use of interrupts.
Agere Systems Inc.
495