tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 520

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Data received from the receive framer is stored in the appropriate channel receive FIFO. In the HDLC mode, the
receiver also places a status of frame byte in the receive FIFO for every complete frame received. The receive
HDLC channel FIFO register bits FRM_HRCOUNT[9:0]
particular channel since the last byte received by the HDLC receive block regardless of how many bytes were read
by the host. The host loads the data from the RFIFO of the various channels through the microprocessor interface.
21.24.10 Transmit HDLC FIFO Features
520
128 bytes of FIFO buffering for each channel with the ability to interrupt on end of packet (EOP), exceed pro-
grammable FIFO threshold or FIFO overrun.
Each channel has independent reset and enable. Reset will reset all state machines, disable the channel, reset
FIFO pointers, and clear pending interrupts. Disabling a channel will reset the state machine but not affect the
FIFO pointers or interrupts.
Any channel can be programmed to run from any combination of bits from any one time slot of either odd or even
(or both) frame numbers of any link.
A loopback mode (from transmit HDLC, through HDLC to FIFO) is supported.
Channels will not operate if the corresponding link/framer goes out of frame (function is equivalent to channel
disabled).
Data is ignored if the link/framer is not in basic frame alignment.
Upon selection from the top level, the 128 bytes of FIFO per-channel can be converted into 512 bytes of FIFO,
with a quarter of the channels.
In transparent mode, simply transform the data to a serial output.
In HDLC mode, correctly format and packetize the outgoing data bits.
In HDLC mode, sends normal packets (close with flag) or abort packets (via command or absence of data).
Provide 128 bytes of FIFO buffering for each channel with ability to interrupt on packet done, below programma-
ble FIFO threshold or underrun (FIFO empty in middle of packet).
Each channel has independent reset and enable. Reset will reset all state machines, disable the channel, reset
FIFO pointers, and clear pending interrupts. Disabling a channel will reset the state machine but not affect the
FIFO pointers or interrupts.
TDM BUS
P CNTL
P ADDR
P DATA
CONVERSION
CHANNEL
TDM TO
Figure 65. Transmit HDLC FIFO Block Diagram
ENABLE
CHAN
INFO
PRM
INTERRUPTS
FIFOs/
INTS.
(Table
446) report the number of bytes available for this
ACK/UNDERFLOW
CHAN
VALID
TYPE
DATA
(continued)
8
PARALLEL-TO-
SERIAL
HDLC/
Agere Systems Inc.
CHAN
LOOPEN
TDMEN
DATA
May 2001
1
5-9029(F)r.1