tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 461

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
20 M13/M23 MUX/DeMUX Block Functional Description
20.5.3 Loopback Select
DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs from the deMUX path to be
looped back. This loopback can be performed automatically if M13_AUTO_FLB
(Table
or E1 loopback by setting M13_SEL_DS1_LBx
When M13_AUTO_LB = 1, loopback of channel x is activated if M13_DS1_LB_DETx = 1
20.11.4 M12 Demultiplexers on page
result of receiving a loopback request through the far-end alarm and control (FEAC) channel. Such a request is
indicated by status bit M13_DS1_FEAC_LB_DETx
bit M13_DS1_FEAC_LB_DETx = 1 and M13_AUTO_FLB = 1, loopback of channel x is activated.
20.5.4 DS1/E1 FIFOs
When M13_M12_MODEy[1] = 0
fed into single bit 16-word-deep FIFOs that are used to synchronize the selected signals to the DS2 frame genera-
tion clock. The DS2/DS3 transmit clock (XC_DS2M12CLKy) is used to derive the clock source for DS2 frame gen-
eration blocks. In the C-bit parity mode, all DS2 stuff opportunities are used, which produces a nominal 6.306 MHz
DS2 clock. In the M23 mode, the DS2 stuffing ratio is fixed such that the DS2 clock is nominally 6.312 MHz.
The fill level of each FIFO determines the need for bit stuffing its DS1/E1 input. This block allows the M13 to accept
DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to 5 unit intervals peak jitter.
When operating in M13_M12_MODEy[1:0] = 10 mode, the FIFOs are not used.
20.6 DS2 Frame Generation
Each M12 MUX generates a DS2 frame either from 4 DS1 signals multiplexed as specified in T1.107 and GR-499-
CORE when M13_DS1_E1Ny = 1
recommendation G.747 when M13_DS1_E1Ny = 0.
When M13_M12_MODEy[1:0] = 01/10
output DS2 signals are retimed by the associated clocks. The edge of the clocks that is used to retime the data is
user provisionable to either the rising edge (M13_DS2M12_EDGEy
(M13_DS2M12_EDGEy = 0). The AIS signal can be inserted into any DS2 output by setting
M13_DS2_FORCE_AISy
20.6.1 DS1 Mode
In the DS1 mode, the 4 signals interleaved to generate the y
selectors 4y – 3, 4y – 2, 4y – 1, and 4y. Bits multiplexed into the second and fourth channels (from selectors 4y – 2
and 4y) are inverted before being interleaved (T1.107) when bit M13_MUXCH2_4_INVy = 1
Loopback requests for a DS1 channel are indicated by inverting the third C bit for that channel (T1.107). This is
done when bit M13_DS1_LB_REQx is set to 1
are 4y – 3, 4y – 2, 4y – 1, and 4y.
The X bit is set to the inverse of the remote alarm indication (RAI) bit (T1.107) M13_DS2_RAI_SENDy
For testing purposes, the M frame alignment signal (normally 011) is generated with the last bit inverted (010) if
M13_DS2_MPINVy is set
M13_DS2_FINVy is set
Agere Systems Inc.
259) bits are set. Regardless of the state of M13_AUTO_FLB and M13_AUTO_LB, the user can force a DS1
(Table
(Table
(Table
268).
(Table
271) to 1.
267), and the M-subframe alignment signal (01) is generated as (00) if
(Table
472). In the C-bit parity mode, automatic loopback can also be activated as a
(Table
263), the 4 selected DS1 or 3 selected E1 signals for each M12 MUX are
263), or from 3 E1 signals multiplexed using the format specified in ITU-T
263), each M12 MUX is operating independently. In this case, the
(Table
(Table
(Table
263). The 4 M13_DS1_LB_REQx bits that affect the y
264) to 1.
251) (see
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
th
DS2 signal are the outputs from DS1/E1 loopback
(Table
Section 20.7.6 FEAC on page
275) = 1) or falling edge
TMXF28155/51 Super Mapper
(continued)
(Table
259) or M13_AUTO_LB
(Table
(Table
249) (see
465). If status
263).
(Table
Section
th
265).
DS2
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