tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 65

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
7 Microprocessor Interface and Global Control and Status Registers
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW)
Agere Systems Inc.
Address
0x00009
14:10
Bit
15
9
8
7
6
5
4
3
2
1
0
SMPR_PMRESET_IM Performance Monitor Reset Interrupt Mask. When this bit
SMPR_SPEMPR_IM
SMPR_PARITY_IM
SMPR_VTMPR_IM
SMPR_TMUX_IM
SMPR_FRM_IM
SMPR_TPG_IM
SMPR_APS_IM
SMPR_M13_IM
SMPR_DJA_IM
SMPR_XC_IM
Name
—
APS Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin APS_INTN.
Reserved.
Microprocessor Interface Data Bus Parity Error Interrupt
Mask. When this bit is set to 1, the composite interrupt bit will
be inhibited from contributing to the interrupt pin INTN.
is set to 1, the composite interrupt bit will be inhibited from
contributing to the interrupt pin INTN.
TPG Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
DJA Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
FRM Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
XC Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
M13 Interrupt Mask. When this bit is set to 1, the composite
interrupt bit will be inhibited from contributing to the interrupt
pin INTN.
VTMPR Interrupt Mask. When this bit is set to 1, the com-
posite interrupt bit will be inhibited from contributing to the
interrupt pin INTN.
SPEMPR Interrupt Mask. When this bit is set to 1, the com-
posite interrupt bit will be inhibited from contributing to the
interrupt pin INTN.
TMUX Interrupt Mask. When this bit is set to 1, the compos-
ite interrupt bit will be inhibited from contributing to the inter-
rupt pin INTN.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
(continued)
Default
0x83FF
Reset
65