tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 70

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers
Table 70. SMPR_CLCR, CDR, and LVDS Control Register (RW)
70
Address
0x00013 15:11
Bit
7:4
10
9
8
3
2
1
0
SMPR_MPU_CDR_MODE CDR Mode Selection. This bit controls the operating
SMPR_MPU_CG_PWRDN PLL Powerdown Selection. This bit controls whether
SMPR_LVDS_REF_SEL
SMPR_PLLPWRDN
SMPR_RXPWRDN
SMPR_CDR_SEL
SMPR_MRESET
Name
—
—
Reserved.
mode of the internal CDR; whether it operates at
155 MHz or 51 MHz.
0 = 155 MHz mode.
1 = 51 MHz mode.
the internal framer PLL is powered on or off.
0 = Internal PLL powered on.
1 = Internal PLL powered off.
LVDS Reference Voltage Selection. This bit controls
which reference voltage, internal or external, is used to
power the LVDS buffers.
0 = External reference voltage is used.
1 = Internal reference voltage is used.
Reserved.
CDR Channel Powerdown. This bit controls the power
to the CDR data channel.
0 = Channel is active, power is on.
1 = Channel is inactive, power to the channel is turned off.
CDR Phase-Lock Loop Powerdown. This bit controls
the power to the CDR PLL circuit.
0 = PLL is active, power to the PLL is turned on.
1 = PLL is inactive, power to the PLL is turned off.
CDR Master Reset. This bit is used for the CDR initial-
ization. It can also be used in test mode to reset test cir-
cuitry.
0 = No reset.
1 = Reset mode.
CDR Selection. This bit controls if the TMUX receives
its high-speed receive clock and data from the on-chip
CDR block or from the pins (bypass the CDR).
0 = Bypass CDR. Receives clock and data directly from
1 = Use CDR. Receives clock and data through CDR.
pins.
Function
Agere Systems Inc.
(continued)
May 2001
0x000C
Default
Reset