nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 107

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
The source and frequency of the clock to the microcontroller system is controlled by the CLKCTRL register:
The source of the 32kHz clock (CLKLF) is controlled by the CLKLFCTRL register:
Revision 1.1
Addr
Addr
0xAD
0xA3
a. Default setting, both oscillators started. Clock sourced from RCOSC16M initially and automatically
a. XOSC16M will be stopped in Deep Sleep and Memory Retention, and therefore, stopping CLKLF in
Note: The CLKCTRL register does not support read-modify-write operations.
switched to XOSC16M
these modes of operation.
Bit
Bit
5:4
2:0
2:0
7
6
3
7
6
5
4
3
R/W
R/W
R/W 1: Keep XOSC16M on in Register retention mode
R/W 1: Clock sourced directly from pin (XC1), bypass oscillators.
R/W 00: Start both XOSC16M and RCOSC16M.
R/W Clock frequency to microcontroller system:
R/W Source for CLKLF:
W
R
R
R
-
-
-
0: Clock sourced by XOSC16M or RCOSC16M, see bit 3
01: Start RCOSC16M only.
10: Start XOSC16M only.
11: Reserved
1: Clock sourced by XOSC16M (that is, XOSC16M active/ running)
0: Clock sourced by RCOSC16M
1: Enable wakeup and interrupt (X16IRQ) from XOSC16M active
0: Disable wakeup and interrupt from XOSC16M active
000: 16 MHz
001:
010:
011:
100:
101:
110:
111:
1: Read CLKLF (phase).
1: CLKLF ready to be used
Reserved
Reserved
Reserved
000: XOSC32K
001: RCOSC32K
010: Synthesized from XOSC16M when active, off otherwise
011: From IO pin used as XC1 to XOSC32K (low amplitude signal)
100: From IO pin (digital rail-to-rail signal)
101: Reserved
110: Reserved
111: None selected
125 kHz
2 MHz
250 kHz
500 kHz
8 MHz
4 MHz
1 MHz
Table 58. CLKLFCTRL register
Table 57. CLKCTRL register
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Function
Function
a
Reset value: 0x00
Reset value: 0x07
a