nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 125

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
The nRF24LE1 contains a true Random Number Generator (RNG), which uses thermal noise to produce a
non-deterministic bitstream. A digital corrector algorithm is employed on the bitstream to remove any bias
toward ‘1’ or ‘0’. The bits are then queued into an 8-bit register for parallel readout.
16.1
16.2
16.3
Write a ‘1’ to the powerUp control bit to start the generator. The resultReady status bit flags when a ran-
dom byte is available for readout in the RNGDAT register. It will be cleared when the data has been read,
and set again when a new byte is ready. An interrupt ( RNGIRQ ) is also produced each time a new byte has
been generated. The behavior of the interrupt is the same as that of the resultReady status bit.
The random data and the resultReady status bit are invalid and should not be used when the RNG is
powered down. When the RNG is powered up, by writing a ‘1’ to the powerUp control bit, the random data
and the resultReady status bit are cleared regardless of whether the random data has been read or not.
It is possible to disable the bias corrector by clearing the correctorEn bit. This offers a substantial speed
advantage, but may yield a statistical distribution that is not perfectly uniform.
The time needed to generate one byte of data is unpredictable, and may vary from one byte to the next.
This is especially true when the corrector is enabled. It takes about 0.1ms on average to generate one byte
when the corrector is disabled, and four times as long when it is enabled. There is an additional start-up
delay of about 0.25ms for the first byte, counted from when the powerUp control bit is set.
Revision 1.1
16
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Non-deterministic architecture based on thermal noise
No seed value required
Non-repeating sequence
Corrector algorithm ensures uniform statistical distribution
Data rate up to 10 kilobytes per second
Operational while the processor is in standby
Random number generator
Features
Block diagram
Functional description
Thermal
source
noise
(RNGCTL)
Figure 56. Block diagram of RNG
Control
register
generator
bitstream
Random
125 of 191
(RNGDAT)
register
Data
corrector
Bias
SFR bus