nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 99

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
The contents of the Interrupt Priority registers define the priority levels for each interrupt source according
to the tables below.
9.4.4
The IRCON register contains Timer 2, SPI, RF, USB and wakeup interrupt request flags.
Revision 1.1
Address Bit
Address Bit
Address Bit
Group
ip1.x
0xA9
0xB9
0xC0
0
1
2
3
4
5
0
0
1
1
Interrupt Request Control Registers – IRCON
Interrupt bits
7:6 Not used
5:0 Interrupt priority. Each bit together with corresponding bit from IP1 register speci-
7:6 Not used
5:0 Interrupt priority. Each bit together with corresponding bit from IP0 register speci-
ip0.x
7
6
5
4
3
2
1
0
ip1.0, ip0.0
ip1.1, ip0.1
ip1.2, ip0.2
ip1.3, ip0.3
ip1.4, ip0.4
ip1.5, ip0.5
0
1
0
1
fies the priority level of the respective interrupt priority group.
fies the priority level of the respective interrupt priority group.
Auto
clear
Yes
Yes
Yes
Yes
Yes
-
-
-
Table 53. Priority levels (x is the number of priority group)
Timer 2 external reload (exf2) interrupt flag
Timer 2 overflow (tf2) interrupt flag
Internal wakeup (TICK) interrupt flag
Miscellaneous (MISCIRQ) interrupt flag
Wakeup on pin (WUOPIRQ) interrupt flag
2-Wire completed (WIRE2IRQ), Master/Slave SPI (MSDONE/SSDONE)
interrupt flag
RF (RFIRQ) interrupt flag
RF SPI ready (RFRDY) interrupt flag
POFIRQ
tf2/exf2
IFP
tf0
tf1
ri0
Table 54. IRCON register
Table 52. Priority groups
Table 50. IP0 register
Table 51. IP1 register
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Description
Description
Level 3 (highest)
Level 0 (lowest)
Priority level
Priority groups
Description
Level 1
Level 2
WUOPIRQ
MSDONE
RFRDY
RFIRQ
TICK
ti0
SSDONE
MISCIRQ