nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 119

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
The MDU – Multiplication Division Unit, is an on-chip arithmetic co-processor which enables the MCU to
perform additional extended arithmetic operations like 32-bit division, 16-bit multiplication, shift and, nor-
malize operations.
14.1
The MDU is controlled by the SFR registers MD0 .. MD5 and ARCON .
14.2
14.3
All operations are unsigned integer operations. The MDU is handled by seven registers, which are memory
mapped as Special Function Registers. The arithmetic unit allows concurrent operations to be performed
independent of the MCU’s activity.
Operands and results are stored in MD0 .. MD5 registers. The module is controlled by the ARCON register.
Any calculation of the MDU overwrites its operands.
The MDU does not allow reentrant code and cannot be used in multiple threads of the main and interrupt
routines at the same time. Use the NOMDU_R515 compile directive to disable MDU operation in possible
conflicting functions.
14.4
The MD0 .. MD5 are registers used in the MDU operation.
Revision 1.1
14
MDU – Multiply Divide Unit
Features
Block diagram
Functional description
SFR registers
Table 66. Multiplication/Division registers MD0..MD5
Address
MDU
Figure 54. Block diagram of MDU
MD0
MD1
ARCON
0xEC
0xED
0xEA
0xEB
0xEE
0xE9
119 of 191
MD2
MD3
Register name
MD0
MD1
MD2
MD3
MD4
MD5
MD4
MD5