nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 155

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
20.2.2.2
RX mode
To enter RX mode, MCU must write the address to the Slave it wants the 2-Wire to connect to, to W2DAT.
7:, and write ‘1’ to the direction bit; W2DAT.0. The byte is then transmitted to the Slave(s). If not masked,
an interrupt request is asserted on the rising edge of SCL following the last bit in the byte. Simultaneously,
the acknowledge from the addressed Slave is stored in W2CON1.1. 2-Wire then releases the control over
the bus and is ready to accept bytewise RX data from the addressed Slave. For each byte received, if not
masked, an interrupt request is asserted at the same time as the last bit is sampled, prior to sending the
acknowledge to the Slave. The acknowledge is also stored in W2CON1.1.
To do a repeated start or stop the transfer, the MCU must set W2CON0.5 after receiving the second to last
byte from the Slave. This makes the 2-Wire Master send a not-acknowledge after the last byte, which
forces the Slave to let go of the bus control. After receiving the last byte, the Master can do a repeated start
by writing a new Slave address and direction bit to W2DAT.
20.2.3
Slave transmitter/receiver
As the 2-Wire Slave detects a start condition it will enter RX mode and wait for the first byte from the Mas-
ter. When the first byte is completed, the Slave compares W2DAT.7 down to W2DAT.1 to W2SADR (or the
general call address, 0x00) to see if it is supposed to reply. If so, W2DAT.0 decides if it should stay in RX
mode (‘0’) or enter TX mode (‘1’).
The 2-Wire Slave asserts interrupt requests to the MCU when 1) there is an address match after a start
condition; 2) after each data byte received (RX mode) or transmitted (TX mode), or; 3) a stop condition is
detected. All interrupts can be masked by configuration.
If the 2-Wire Slave’s MCU has trouble processing the data fast enough, it can stall the transmission by set-
ting W2CON0.6 to ‘1’ between bytes. In TX mode, this forces SCL ‘low’ after transmission until the MCU
has written new data to W2DAT. In RX mode, SCL is kept ‘low’ after reception, until the MCU has read the
new data.
New TX data must always be written by the MCU to W2DAT before the next falling edge on SCL.
New RX data must always be read by the MCU from W2DAT before the next rising edge on SCL, after the
corresponding interrupt request.
Revision 1.1
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