nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 122

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nrf24le1-f16q48-t

Manufacturer Part Number
nrf24le1-f16q48-t
Description
Ultra-low Power Wireless System On-chip Solution
Manufacturer
ETC-unknow
Datasheet
nRF24LE1 Preliminary Product Specification
The error flag is set when:
The error flag is reset only after read access to the ARCON register. The error flag is read only.
14.4.7
The mdov overflow flag (see
Any operation of the MDU that does not match the above conditions clears the overflow flag.
Revision 1.1
If you write to MD0.. MD5 and/or ARCON during phase two of MDU operation (restart or calculations
If any of the MDx registers are read during phase two of MDU operation when the error flag mecha-
nism is enabled. In this case, the error flag is set but the calculation is not interrupted.
division by zero.
multiplication with a result greater than 0000 FFFFh.
start of normalizing if the most significant bit of MD3 is set (“md3.7” = ‘1’).
Note: The overflow flag is exclusively controlled by hardware, it cannot be written.
interrupting).
The mdov flag
Table 67. on page
120) is set when one of the following conditions occurs:
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