nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 76

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
When the programming code executes from the flash, erase or write operation is self timed and the CPU
stops until the operation is finished. If the programming code executes from the XDATA RAM the code
must wait until the operation has finished. This can be done either by polling the RDYN bit in the FSR regis-
ter to go low or by a wait loop. Do not set WEN low before the write or erase operation is finished. Memory
address is identical to the flash address, see
6.3.4
The on-chip flash is designed to interface a standard SPI device for programming. The interface uses an 8
bit instruction register and a set of instructions/commands to program and configure the flash memory.
6.3.4.1
To program the memory a the SPI slave interface is used. SPI slave connection to the flash memory is acti-
vated by setting pin PROG = 1 while the reset pin is kept inactive. When the PROG pin is set, selected
nRF24LE1 GPIO pins are automatically configured as a SPI slave as shown in Table 32. Further informa-
tion on SPI slave timing can be found in chapter 18 on page 142
The program interface uses an 8 bit instruction register and a set of instructions/commands to program
and configure the flash memory.
Revision 1.1
Command
PROGRAM
Note: After activation of the PROG pin you must wait at least 1.5 ms before you input the first flash
WRDIS
WREN
WRSR
RDSR
READ
FMISO
FMOSI
Flash programming through SPI
FCSN
FSCK
command.
Table 32. Flash SPI slave physical interface for each nRF24LE1 package alternative
SPI slave interface
Command
format
0x06
0x04
0x05
0x01
0x03
0x02
24pin-4x4
P0.5
P0.4
P0.3
P0.2
2 bytes, first
address to
address to
to be read
First flash
be written
Address
2 bytes,
flash
5 on page 62
NA
NA
NA
NA
76 of 191
1-18432
1-18432
# Data
bytes
XX
XX
0
0
1
1
for memory mapping.
32pin-5x5
P1.1
P1.0
P0.7
P0.5
Write FLASH Status Register (FSR).
Set flash write enable latch.
Bit WEN register FSR
Reset flash write enable latch.
Bit WEN in register FSR
Read FLASH Status Register (FSR)
Read data from FLASH
Write data to FLASH
Note: WEN must be set.
Note: The DBG bit in FSR can
Command operation
only be set by the MCU
48pin-7x7
P2.0
P1.6
P1.5
P1.2