nrf24le1-f16q48-t ETC-unknow, nrf24le1-f16q48-t Datasheet - Page 78

• Manufacturer Part Number: nrf24le1-f16q48-t
• Description: Ultra-low Power Wireless System On-chip Solution
• Manufacturer: ETC-unknow

nRF24LE1 Preliminary Product Specification
WREN / WRDIS flash write enable/disable:
SPI commands WREN and WRDIS sets and resets the flash write enable latch WEN in register FSR. This
latch enables all write and erase operations in the flash blocks.
The device will power-up in write disable state, and automatically go back to write disable state after each
write/erase SPI command (FCSN set high). Each erase and write command over the SPI interface must
therefore be preceded by a WREN command.
Both WREN and WRDIS are a 1 byte SPI command with no data.
RDSR / WRSR read/write flash status register
SPI commands RDSR and WRSR read and writes to the flash status register FSR. Both commands are 1
are followed by a data byte for the FSR content, see Figure 33. and Figure 34.
READ
SPI command READ reads out the content of an addressed position in the flash main block. It must be fol-
lowed by 2 bytes denoting the start address of the read operation, see Figure 33. If bit INFEN in register
FSR is enabled, the read operation will be conducted from the InfoPage instead.
Revision 1.1
FMOSI
FMOSI
FMISO
FMISO
FCSN
FSCK
FCSN
FSCK
C7
C7
Figure 34. SPI write operations for direct and addressed commands.
Abbreviations
C6
C6
C5
C5
C4
C4
Cx
Ax
Dx
C3
C3
C2
C2
Table 34. Flash SPI interface signal abbreviations
C1
C1
C0
C0
A7
D7
A6
D6 D5
SPI Command bit
Flash address. Sequence LS to MS byte, MS to LS
bit.
SPI data bit, Sequence LS to MS byte, MS to LS
bit. Presence depending on SPI command.
A5
Optional
A4
D4
A3
D3
78 of 191
A2
D2
A1
D1
D0
A0
A15
Description
A14 A13 A12 A11 A10 A9
A8
D7
D6
D5
D4
D3
D2
D1
D0