SC16C554BIB64 PHILIPS [NXP Semiconductors], SC16C554BIB64 Datasheet - Page 20

• Manufacturer Part Number: SC16C554BIB64
• Description: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 13133
Product data sheet
6.7 DMA operation
6.8 Loop-back mode
The SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C554B/554DB activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the preset trigger level. In this
mode, the SC16C554B/554DB sets the interrupt output pin when the characters in the
receive FIFOs are above the receive trigger level.
The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally.
MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the
loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and
CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the
modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally (see
disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit
holding register via the user data bus interface, D0 to D7. The transmit UART serializes
the data and passes the serial data to the receive UART via the internal loop-back
connection. The receive UART converts the serial data back into parallel data that is then
made available at the user data interface D0 to D7. The user optionally compares the
received data to the initial transmitted data for verifying error-free operation of the UART
TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status
Register bits 4:7. The interrupts are still controlled by the IER.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Rev. 01 — 9 February 2005
Figure
12). The CTS, DSR, CD, and RI are
SC16C554B/554DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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