SC16C554BIB64 PHILIPS [NXP Semiconductors], SC16C554BIB64 Datasheet - Page 37

• Manufacturer Part Number: SC16C554BIB64
• Description: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 26:
T
[1]
[2]
[3]
9397 750 13133
Product data sheet
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
N
28d
30s
30w
30h
30d
31d
31h
32s
32h
32d
33s
33h
RESET
amb
Fig 14. General read timing in 68 mode
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
= 40 C to +85 C; V
delay from start to reset
TXRDY
address setup time
chip select strobe width
address hold time
read cycle delay
delay from CS to data
data disable time
write strobe setup time
write strobe hold time
write cycle delay
data setup time
data hold time
RESET pulse width
baud rate divisor
A0 to A4
D0 to D7
Dynamic characteristics
R/W
CS
10.1 Timing diagrams
-------
t
3w
1
CC
t
32s
t
= 2.5 V, 3.3 V or 5.0 V
30s
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
…continued
t
31d
t
30w
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Rev. 01 — 9 February 2005
[1]
10 %, unless otherwise specified.
Min
-
10
90
15
20
-
-
10
10
25
20
15
200
1 T
[3]
RCLK
t
30h
t
31h
2.5 V
Max
8 T
-
-
-
-
90
15
-
-
-
-
-
-
2
T
[3]
16
RCLK
t
RCLK
30d
1
[3]
Min
-
10
26
15
20
-
-
10
10
25
15
5
40
1 T
[3]
SC16C554B/554DB
RCLK
3.3 V
Max
8 T
-
-
-
-
26
15
-
-
-
-
-
-
2
T
[3]
16
RCLK
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
RCLK
1
[3]
Min
-
10
23
15
20
-
-
10
10
20
15
5
40
1 T
[3]
RCLK
5.0 V
002aaa210
Max
8 T
-
-
-
-
23
15
-
-
-
-
-
-
2
T
[3]
16
RCLK
RCLK
1
[3]
37 of 51
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns