SC16C554BIB64 PHILIPS [NXP Semiconductors], SC16C554BIB64 Datasheet - Page 26

• Manufacturer Part Number: SC16C554BIB64
• Description: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 13133
Product data sheet
7.3.2 FIFO mode
Table 11:
Bit
7:6
5:4
3
2
1
0
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
Not used; initialized to logic 0.
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C554B/554DB is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C554B/554DB is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1; FCR[3] =
logic 0) and there is at least one character in the receive FIFO, the RXRDY
pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when
there are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C554B/554DB is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a logic 0 if one or more
FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C554B/554DB is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-out has occurred, the RXRDY pin will go to a
logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
Rev. 01 — 9 February 2005
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
Table
12.
SC16C554B/554DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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