STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet
STLC5432Q
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STLC5432Q Summary of contents
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... STLC5432 can work either in 2048 or 4096 or 8192 Kbit/s systems programming the CR4 regis- ter (when parallel micro interface selected). July 1996 STLC5432 PRELIMINARY DATA TQFP44 (10 x 10) ORDERING NUMBER: STLC5432Q PIN CONNECTION (Top view ...
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STLC5432 PIN DESCRIPTION Name Pin Type VCCD1 18 I Positive power supply inputs for the digital (V VCCD2 17 I microprocessor interface signals (V VCCA 34 I connected together. GNDD 1 I Negative power supply pins which must be connected ...
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PIN DESCRIPTION (continued) Name Pin Type LCLK 23 I Local Clock : this clock input determines the data shift rate on the two digital multiplexes. This clock frequency can be indifferently 2048, 4096, 8192 or 16384kHz. Data Out and Data ...
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STLC5432 BLOCK DIAGRAM 4/46 ...
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ABSOLUTE MAXIMUM RATINGS Symbol V to GND Supply Voltage to Ground CC V Voltage at any digital or analog input Current at LO1 and LO2 LO1 OL2 I Current at any digital or analog input C ...
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STLC5432 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter POWER CONSUMPTION Icc75 Active Current (including line current) Icc120 Active Current (including line current) TRANSFORMER SPECIFICATION FOR 75 L:M:N: Turns ratioes RL L Windings Resistance RMN M and N winding resistances LL Inductance of ...
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Figure 1: Receiver Diagram STLC5432 7/46 ...
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STLC5432 INTRODUCTION This single chip CMOS Device interfaces the physical multiplex of the application to the physi- cal CEPT transmission link at 2048kb/s. STLC5432 contains analog and digital functions to implement line interface function and frame synchronization. It meets pulse ...
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Using both options allow the reception of a signal attenuated up to 12dB at 1024kHz. The Clock recovery is performed by a first PLL that guaranties the CCITT I431 requirements for the allowed Jitter, see Figure 23, this clock, RCL, ...
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STLC5432 XCLK (respectively Transmit Data and its clock associated). Frame and multiframe generated by the transmitter of the circuit are processed by the receiver of the circuit, without encoding and de- coding. 4.4 LOOPBACK 4 LP4 Command replaces Data in ...
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Typical case Remote entity transmits Frame Alignment Signal (FAS) and Multiframe Alignment Signal (MFAS). As soon as lost of Frame Alignment is occured (LOF = 1), the local receiver recovers FAS from 254 up to 500 s after. As ...
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STLC5432 R Message to write a register, addressed by the bits A0/5. The bit 7 of following byte is 1 and the seven D 0/6 bits are data to load into register. To transfer one message, 250 s ...
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Serial Interface Mode When an Alarm bit is put ALR (Alarm Reg- ister), this bit generates automatically the trans- mission of two bytes message onto DOUT during Time slot 0 with : – The first bit ...
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STLC5432 Table 3: The registers and their bits. After ADD Register Reset bit 7 bit 6 (Dec.) Name (Hexa RESET ALR 1 EXT1 3 FF AMR 1 MEXT1 4 80 CAR1 1 EXT2 5 FF ...
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Reset Register 7 1 Dummy Register The software reset of the circuit is performed when this register is addressed whatever the value of its bits may be. Reading or writing is ir- relevant. All the programmable registers are con- ...
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STLC5432 When a bit of this register is at ”1”, the CAR1 Register bit which has the same number is masked. The CAR1 bit which is masked do not generate an interrupt. 9.6 CAR2: Complementary Alarm Register ...
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PCR1: PRS Counter Register After Reset = 80H P0/6 7 less significant bits of the Pseudo Random Counter Register. 9.13 PCR2: PRS Counter Register P13 P12 P11 P10 ...
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STLC5432 9.18 TS0XR: Time Slot Zero transmit Register Sa4X Sa5X Sa6X Sa7X Sa8X After Reset = 9FH Sa4X to Sa8X Bits each odd Time Slot Zero to be transmitted onto the line ...
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LP4 Loopback 4 When this bit is at ”1”, loop back 4 is validated during Time Slot selected. The loop back is located between DOUT and DIN pins. The loop back is transparent during the Time Slot selected. DOUT always ...
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STLC5432 9.23 CR1: Configuration Register MERA LTM 8KCR MCR1 MCR0 SELEX SELER After Reset = 84H SELER Selection of an external signal side receiver. When SELER=1, the internal binary data signal and its clock associated are replaced ...
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RDS0/1Receive Data Select Bit 0/1 When the PRS analyser is validated SAV = 1 (TCR2), Sequence is checked by the analyser during the Time Slot(s) selected by TCR2. RDS1 RDS0 Source 0 0 Sequence comes from Memory input ...
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STLC5432 When DEL is at ”0”, Bit 0 of TS0 is indicated by the rising edge of Frame synchronization signal. When DEL is at ”1”, Bit 0 of TS0 is delayed; the rising edge of Frame Synchronization indicates the bit ...
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CR5 Configuration Register TS0E APD NMF HCRD DPIS CENTER FROZ After Reset = 80H FROZ Frozen DPLL. FROZ = 1, the DPLL is immediately frozen. Id est: DPLL retains its phase and its frequency while FROZ ...
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STLC5432 Transmitter side: SaT fixs the number of consencutive transmissions of Sa61 to Sa64 bits onto the line before resetting WT (Sa6XR register). See definition of WT bit in chapter 9.19 OSCD Oscillator Disabled OSCD = 1, The clock pulse ...
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TCR1: Test Configuration Register SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0 After Reset = 80H GTS0 to GTS5 Time Slot associated to generator. These 6 bits indicate Time Slot(s) selected to transmit the Pseudo Random Binary ...
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STLC5432 9.34 TCR3 Test Configuration Register CRCC EBC PELC PULS FASC ODTS TWI After Reset = 80H TWI TSO corrupted TWICE. If FASC=1 and TWI=1, Time Slot 0 selected by ODTS is corrupted twice only. If FASC=1 ...
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Figure 3: Connections with and without Internal Equalizer. (*) 60 Zc=120 60 100nF Zc=120 15 (*) To be inserted for the internal Equalizer Figure 4: STLC5432 Line Interface Configurations (CEPT 120 ...
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STLC5432 Figure 5: Main Alarm Processing LINE STATE RECEIVING ALARMS ALARMS TRANSMITTED DETECTED ODD TS0 BIT 3 Ax LOS AIS 915 LOF AR WER Figure 6: DIN and DOUT During Time slot 0. SA pin: 0V Serial Interface Parallel Interface: ...
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Figure 6a: DOUT during Timeslot 0 (Bits when TS0E = 1 (CR5) Without skip Odd frame ODD = 1 SKIP = 0 SLC = X With skip and loss of Even frame n Odd ...
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STLC5432 Figure 7: DIN/DOUT multiplex during Time Slot 0 - Serial Microprocessor Interface Mode. BIT NUMBER ADDRESS REGISTER DATA 1 IDLE THE BITS ARE TRANSMITTED TO MULTIPLEX IN ORDER, BIT 1 FIRST TWO ...
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Figure 8: Jitter Transfer Characteristic (CCITT I431) Gain (dB Carrier frequency (logarithmic scale –19.5dB 0.5dB Figure 9: Level 1 - Level 2 Process with Parallel Interface P. 2Mb/s LEVEL 1 S2/T2 PRCD PARALLEL ...
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STLC5432 Figure 10: Primary Rate Controller Device PRCD - TE mode with serial Microprocessor XTAL1 2Mb/s RECEIVER INTERFACE S2/T2 LTM=0 (Configuration Register1) Figure 11: Four STLC5432 in LT Mode MASTER CLOCK 32764KHz XTAL1 STLC5432 XTAL1 STLC5432 XTAL1 STLC5432 XTAL1 STLC5432 ...
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Figure 12: ETSI NT1 Option 2 STLC5432 33/46 ...
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STLC5432 Figure 13: Synchronization Algorithm LOF = 1 LOSS OF FRAME DOUT DELIVERS ”ALL 1s” FRAME RESEARCH FRAME NO ALIGNMENT RECOVERY YES LOF = 0 DOUT IS VALIDATED. TIMER OUT 400ms STARTS. MULTIFRAME RESEARCH ...
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Figure 14: Three Cases of Synchronization. TYPICAL CASE LOF 500 s max MFR MFNR OLD EXISTING EQUIPMENT CASE LOF 500 s max MFR MFNR PARTICULAR CASE: SPURIOUS FAS LOF 500 s max MFR MFNR STLC5432 6ms max 400ms max 8ms ...
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STLC5432 Figure 15: Pseudo Random Sequence Analyzer Algorithm. START SAV =1 PRS DURING ALL THE TIME SLOTS NO LOF = 1 SAV SEQUENCE ANALYZER VALIDATED LOF LOSS OF FRAME MFR MULTIFRAME RECOVERED MFNR MULTIFRAME NOT RECOVERED PRSR PSEUDO RANDOM SEQUENCE ...
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Figure 16: Transmitter Side Timing SIG = 0 DATA RATE AT 2048Kb/s LCLK (CLOCK) tpd BXDO (DATA) BXDI (DATA) SIG = 1 DATA RATE AT 64Kb/s BXDO (CLOCK) BXDI (DATA) Figure 16a: Transmitter Side: Delay on BXD0 pin Example applied ...
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STLC5432 Figure 17: Receiver Side Timing T1/2 RCLO (CLOCK BRDO (DATA) RCLI (CLOCK) BRDI (DATA) SIG = 488ns 61 (2048Kb/s) SIG = 15 (64Kb/s) T’ = 488ns 61 (RCLI e ...
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Figure 18a: High Clock and Low Clock in LT and TE Mode XTAL1 LT MODE ONLY { tpd THCR/2 HCR LCR td td 8MCR 1 (8MHz) 0 (4MHz) LTM = 1 LT MODE HCR AND LCR ARE GENERATED BY CLOCK ...
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STLC5432 Figure 20: Single Clock Delayed Mode. LCLK LFSX LFSR DOUT DIN DCP = 0 SINGLE PULSE T = 488ns MULTIPLEX AT 2Mb 244ns MULTIPLEX AT 4Mb 122ns MULTIPLEX AT 8Mb/s DEL = 0 NOT DELAYED ...
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Figure 22: CCITT G703 HDB3 Pulse Template 10% V=100% 10% 50% 10% 0% 10% D93TL068 Figure 23: Allowed Jitter at the TE and LT Inputs (CCITT I431) PEAK TO PEAK JITTER AMPLITUDE (UI 20.5 ...
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STLC5432 Multiplexed Motorola-like P bus timing. ( 5V) t WAS AAS ADDRESS AD0/7 Signal name Corresponding pin AS AS/ALE (13) DS DS/RD (21) R/W R/W/WR (26 (35) A/D0 to ...
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Multiplexed ST9-like P bus timing. ( WAS DS R AAS ADDRESS AD0/7 VALID Signal name Corresponding pin AS AS/ALE (13) DS DS/RD (21) R/W R/W/WR (26 (35) A/D0 to ...
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STLC5432 Multiplexed Intel-like P bus timing. ( 5V) READ CYCLE t WA ALE CS. ADDR WRITE CYCLE CS.WR AD0/7 READ CYCLE (Multiplexed Intel Mode) Symbol Parameter t Address Hold After ALE LA ...
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TQFP44 (10 x 10) PACKAGE MECHANICAL DATA DIM. MIN. TYP 0.05 A2 1.35 1.40 B 0.30 0.37 C 0.09 D 12.00 D1 10.00 D3 8.00 e 0.80 E 12.00 E1 10.00 E3 8.00 L 0.45 0. ...
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STLC5432 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...