ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 14

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

ADV7340/ADV7341
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Y OUTPUT
P_HSYNC
P_BLANK
C9 TO C2/
Y9 TO Y2/
P_VSYNC
C9 TO C0
Y9 TO Y0
Figure 13. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)
CONTROL
OUTPUTS
Y9 TO Y2/
Y9 TO Y0
CLKIN_A
Figure 14. ED-SDR, 16-/20-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
t
11
3FF
t
9
t
a
12
t
10
c
00
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00
XY
t
14
t
13
b
Cb0
Y0
Cr0
Cb0
Y0
Y1
Cr0
Y1
Cb2
Y2
Cr2
Y3