ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 32
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ADV7340EBZ
Manufacturer Part Number
ADV7340EBZ
Description
Manufacturer
AD [Analog Devices]
Datasheet
1.ADV7340EBZ.pdf
(88 pages)
- Current page: 32 of 88
- Download datasheet (2Mb)
ADV7340/ADV7341
Table 18. Register 0x30
SR7 to
SR0
0x30
1
Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
Register
ED/HD Mode
Register 1
Bit Description
ED/HD Output
Standard.
ED/HD Input
Synchronization
Format.
ED/HD Input Mode.
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
10011–11111
6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
Rev. 0 | Page 32 of 88
Bit Number
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2
0
1
1
0
0
1
1
0
0
1
0
1
Register Setting
EIA770.2 output.
EIA770.3 output.
EIA770.1 output.
Output levels for full
input range.
Reserved.
External HSYNC , VSYNC
and field inputs.
Embedded EAV/SAV
codes.
SMPTE 293M,
ITU-BT.1358.
Nonstandard timing mode.
BTA-1004, ITU-BT.1362.
ITU-BT.1358.
ITU-BT.1362.
SMPTE 296M-1,
SMPTE 274M-2.
SMPTE 296M-3.
SMPTE 296M-4,
SMPTE 274M-5.
SMPTE 296M-6.
SMPTE 296M-7,
SMPTE 296M-8.
SMPTE 240M.
Reserved.
Reserved.
SMPTE 274M-4,
SMPTE 274M-5.
SMPTE 274M-6.
SMPTE 274M-7,
SMPTE 274M-8.
SMPTE 274M-9.
SMPTE 274M-10,
SMPTE 274M-11.
ITU-R BT.709-5.
Reserved.
1
Note
ED
HD
525p @ 59.94 Hz
525p @ 59.94 Hz
625p @ 50 Hz
625p @ 50 Hz
720p @ 60/59.94 Hz
720p @ 50 Hz
720p @ 30/29.97 Hz
720p @ 25 Hz
720p @ 24/23.98 Hz
1035i @ 60/59.94 Hz
1080i @ 30/29.97 Hz
1080i @ 25 Hz
1080p @ 0/29.97 Hz
1080p @ 25 Hz
1080p @ 4/23.98 Hz
1080Psf @ 24 Hz
Reset
Value
0x00
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